A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Field effect transistors, such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), are now widely used within integrated circuits. As the dimensions of the MOSFET are further scaled down to submicron and nanometer dimensions, the thickness of the gate oxide of the MOSFET is also scaled down accordingly. However, a thin gate oxide for a MOSFET of submicron and nanometer dimensions is leaky due to charge carrier tunneling and leads to faster degradation of the MOSFET. Thus, an alternative gate dielectric having a high dielectric constant, such as a metal oxide, is used to replace the gate oxide for a MOSFET of submicron and nanometer dimensions.
A gate dielectric having a high dielectric constant, such as a metal oxide, however, may not be stable during fabrication processes using relatively high temperatures. For example, a dopant activation anneal or a salicidation anneal for the source, the drain, and the gate of a MOSFET may be performed at temperatures over 1000.degree. Celsius. At such a high temperature, a gate dielectric having a high dielectric constant may not be thermally stable. For example, tantalum oxide (Ta.sub.2 O.sub.5), an example of a gate dielectric having a high dielectric constant, changes phase from being amorphous to being crystalline at temperatures above 800.degree. Celsius. In a crystalline phase, tantalum oxide (Ta.sub.2 O.sub.5) is undesirably leaky. In addition, at such a high temperature, a gate dielectric having a high dielectric constant may undesirably react with the silicon of the channel region of the MOSFET or the polysilicon of the gate of the MOSFET.
In the prior art, as discussed in the technical journal article with title Sub-100 nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process by A. Chatterjee et al., IEDM, 1997, pages 821-824, a metal gate electrode is fabricated with a gate dielectric having a high dielectric constant after any fabrication process using a relatively high temperature. However, such prior art uses only a single type of metal gate for both a P-channel MOSFET and an N-channel MOSFET.
Unfortunately, a single mid-band material such as metal for the gate electrode of both a P-channel MOSFET and an N-channel MOSFET is disadvantageous as the MOSFET is scaled down to submicron and nanometer dimensions. Short channel effects may become severe for a MOSFET having channel lengths of tens of nanometers when one type of metal gate is used for both the P-channel MOSFET and the N-channel MOSFET. In addition, a metal gate is disadvantageous because the metal from the gate may diffuse into the gate dielectric causing faster degradation of the gate dielectric having the high dielectric constant, or the metal from the gate may penetrate through the gate dielectric into the channel region of the MOSFET to further degrade the MOSFET reliability.
Nevertheless, further scaling down of MOSFET dimensions is desired. Thus, a process is desired which effectively fabricates N-channel MOSFETs and P-channel MOSFETs having dual gates for these two different MOSFETs with gate dielectrics of high dielectric constant. Dual gates for the two different types of MOSFETs alleviate short channel effects as the dimensions of the MOSFET are scaled down to tens of nanometers, and at the same time, such a process incorporates a gate dielectric of the high dielectric constant to replace the leaky gate oxide of thin dimensions.
For fabrication of dual gates for the P-channel MOSFET and the N-channel MOSFET, an amorphous semiconductor material, such as amorphous silicon, is deposited for forming the gate electrode, and the amorphous semiconductor material is doped with a P-type dopant for the P-channel MOSFET and with an N-type dopant for the N-channel MOSFET. After such doping of the amorphous semiconductor material of the gate, the amorphous semiconductor material is heated to activate the P-type dopant for the P-channel MOSFET and the N-type dopant for the N-channel MOSFET. To preserve the integrity of the gate dielectric having the high dielectric constant, it is desired to use a temperature that is as low as possible during such heating of the amorphous semiconductor material of the gate of the MOSFET.